Device and method for etching flash memory gate stacks comprising high-k dielectric

ABSTRACT

In one implementation, a method for etching a flash memory high-k gate stack on a workpiece is provided which includes etching a conductive material layer in a low temperature plasma chamber and etching a high-k dielectric layer in a high temperature plasma chamber. The workpiece is transferred between the low temperature plasma chamber and the high temperature plasma chamber through a vacuum transfer chamber connecting the low temperature plasma chamber and the high temperature plasma chamber. In one embodiment, an integrated etch station for etching a high-k flash memory structure is provided, which includes an etch chamber configured for plasma etch processing of a conductive material layer connected via a transfer chamber to an etch chamber configured for plasma etch processing of a high-k dielectric layer.

CROSS REFERENCE TO RELATED APPLICATION

The present application is a continuation of pending U.S. applicationSer. No. 11/386,054, filed Mar. 21, 2006; by Shen et al. entitled DEVICEAND METHOD FOR ETCHING FLASH MEMORY GATE STACKS COMPRISING HIGH-KDIELECTRIC, herein incorporated by reference in its entirety.

BACKGROUND

Integrated circuits (IC) play a significant role in the field of modernsemiconductor technology. The development of integrated circuits hasmade possible a modern world with advanced electrical technology.Applications of integrated circuits are so widespread and theirsignificance affects our every day lives from cellular phones, digitaltelevisions, to flash memory chips in cameras. These integrated circuitstypically are formed on silicon substrates or wafers, which can includeactive semiconductor devices with structured processes for a wide rangeof stacked layers made from different materials, allowing for memorycapabilities.

Recently, in modern semiconductor technology, integrated circuits haveadvanced towards smaller devices with more memory. In the manufacture ofsemiconductor integrated circuits (IC), typically, dielectric materialssuch as silicon dioxide (SiO₂), silicon nitride (Si₃N₄) and siliconoxynitride (SiON) have been widely used. However, as technology hasprogressed, IC device geometry has become smaller, resulting inprogressively thinner integrated circuit devices. When typical ICdevices approach thicknesses of a few nanometers or less, conventionalaforementioned dielectric materials can typically undergo electronicbreakdown and can no longer provide the memory storage needed.

To address the aforementioned problems, high dielectric constantmaterials (high k dielectric materials) have been used in semiconductorchip manufacturing with their potential application in memory devices,such as flash memory. A conventional flash memory film stack consists ofpoly 2 (control gate)/ONO (interpoly dielectric)/poly 1 (floating gate)gate oxide. One of the key changes in the gate film stack at 65nanometer node and beyond, for flash memory applications, is thereplacement of the ONO inter-poly dielectric film with a high-kmaterial. Examples of high-k materials include aluminum oxide, (Al₂O₃),hafnium oxide (HfO_(x)), zirconium oxide (ZrO_(x)), titanium oxide(TiO_(x)), and mixtures thereof, and metal silicates such asHfSi_(x)O_(y), ZrSiO₄ and mixtures thereof.

Because of the different composition and reduced size of the high-kdielectric flash memory stack, processing can not be efficiently carriedout with conventional etch chamber processing. Therefore, what is neededis an etch chamber and processing methods designed for efficientprocessing of high-k dielectric flash memory stacks.

SUMMARY

In one implementation, a method for etching a flash memory high-k gatestack on a workpiece is provided which includes etching a conductivematerial layer in a low temperature plasma chamber and etching a high-kdielectric layer in a high temperature plasma chamber. The workpiece istransferred between the low temperature plasma chamber and the hightemperature plasma chamber through a vacuum transfer chamber connectingthe low temperature plasma chamber and the high temperature plasmachamber.

In one embodiment, an integrated etch station for etching a high-k flashmemory structure is provided, which includes an etch chamber configuredfor plasma etch processing of a conductive material layer connected viaa transfer chamber to an etch chamber configured for plasma etchprocessing of a high-k dielectric layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a simplified example of an etched flash memory stack on asubstrate.

FIG. 2 shows a simplified illustration of a two chamber etch system foretching a high-k flash memory stack.

DESCRIPTION

FIG. 1 shows a simplified example of an etched flash memory stack 100 ona substrate 160. A hardmask 110 in an etch process to define the stack100. A high-k dielectric 130 is located between a control gate 120 and afloating gate 140. The control gate 120 and the floating gate 140 may beetched from polysilicon layers, or layers of other conducting material(not shown). The high-k dielectric 130 is defined from a layer (notshown) of high-k dielectric material after the control gate 120 isdefined. A gate oxide 150 is between the floating gate 140 and thesubstrate 160. The stack 100 may include additional layers, not shown,such as barrier layers, etch stop layers, or the like.

A conventional ONO-based flash memory gate stack is etched in a chamberlike a DPSII poly etcher, manufactured by Applied Materials, Inc., ofSanta Clara, Calif., at temperatures between 40-85 degrees Celsius. Thetemperature requirement primarily is driven by need to etch polysiliconwith tight profile and critical dimension control.

Unlike ONO (SiO₂/SiN/SiO₂ sandwich) films, high-k material films such asAl₂O₃ and HfO_(x), for example, are very difficult to etch attemperatures below 100 degrees Celsius because the etch byproducts arenon-volatile. Hence it is not practical to carry out the complete gateetch for high-k based flash memory stacks 100 in a single lowtemperature chamber.

FIG. 2 shows a simplified illustration of a two chamber etch system 200for etching a high-k flash memory stack. Referring to FIGS. 1 and 2, ina first chamber 210 an etch is performed with a cathode 210 c at atemperature below about 100 degrees Celsius to define a control gate 120from a poly 2 layer or other conducting layer. The etch is stopped atthe high-k dielectric material. The first chamber 210 may be a DPSIIetch chamber available from Applied Materials, Inc.

The wafer 202 is transported through a vacuum transport chamber 240,which typically has a wafer transport means such as a robotic arm (notshown), to a second chamber 220, where a high-k dielectric etch isperformed. This process is typically controlled by a microprocessor (notshown). In the second chamber 220 the high-k dielectric etch isperformed using a hot cathode 220 c with a temperature in a range fromabout 100 degrees Celsius to about 300 degrees Celsius. In someimplementations, the high-k dielectric etch is performed using a hotcathode 220 c with a temperature in a range from about 250 degreesCelsius to about 300 degrees Celsius. The high-k etch defines the high-kdielectric 130 shown in FIG. 1. In the second etch chamber 220, thehigh-k material film may be etched with up to 700% over etch. ADPSII-HT, available from Applied Materials, Inc., or other comparableetch chamber may be used to perform the high-k dielectric etch.

In another embodiment, the second etch chamber 220 is a reactive ionetch or RIE chamber, which is used to perform an ion bombardmentassisted chemical etch of the high-k material. Such an etch may beperformed at less than 100 degrees Celsius, if desired.

In one example implementation, a high-k material such as Al₂O₃ may beetched with a reactant mixture having BCl₃ and a hydrocarbon passivationgas such as C₂H₄, with a diluent of He, as disclosed in U.S. patentapplication Ser. No. 11/208,573, by Wang et al., entitled METHOD FORETCHING HIGH DIELECTRIC CONSTANT MATERIALS, filed Aug. 22, 2005, hereinincorporated by reference in its entirety. In one implementation, a hightemperature etch at greater than about 150 degrees Celsius may be usedwith a BCl₃ based chemistry, to provide high selectivity, with a nearvertical Al₂O₃ interface and virtually no control gate poly attack.Thus, a greater than 1.5 to 1 selectivity between the Al₂O₃ and polyduring the Al₂O₃ etch is possible. In another example, a high-k materialsuch as hafnium oxide may be etched using 250 degrees Celsius, orhigher.

After etching the high-k dielectric 130, the wafer 202 is returned backto the first chamber 210 to complete etching of the floating gate 140.The etch is stopped on the gate oxide 150. The floating gate 140 may bea poly 1 or other conducting material.

Various embodiments may provide one or more advantages in high-k flashmemory processing. Using a separate chamber for the high-k dielectricetch allows high temperature etching by forming volatile etchbyproducts. For example, CF₄, C₂F₆, CHF₃ chemistries can provide highetch selectivity in conventional processing. When used to etch high-kmaterials, these etchant gases combine to form non-volatile compounds,such as AlF₃ in the case of Al₃O₂ high-k dielectric. Thus, anotherchemistry that forms volatile etch byproducts, such as Cl, could be usedto etch the high-k material.

Further, by using separate chambers for the control and/or floating gate120 and 140 etch, and the high-k dielectric 130, it is easier tomaintain consistent chamber conditions and wall effects from wafer towafer, enabling volume production. Moreover, using separate chambers forthe etching of flash memory stacks allows different plasma generationsources for the two chambers, one optimized for etching gate materialsand the other for etching high-k dielectric materials. In contrast,etching the entire flash memory stack 100 in a single chamber canproduce undesirable etch byproducts. For example, etching a high-k filmof Al₂O₃ and a gate electrode film of polysilicon in the same chambercan result in Al and Si based etch byproducts in the chamber. Keeping asingle chamber clean to achieve consistent chamber performance and ahigh mean wafer between cleaning or MWBC rate is not easy in a singlechamber. Using different chambers for etching the high-k material andthe gate material limits the types of byproducts, so improves processconsistency and the MWBC rate. By using a separate first chamber 210 forthe polysilicon for example, a standard clean process may be used in thefirst chamber 210, and a different clean process may be used for thehigh-k dielectric byproducts in the second chamber 220, depending on theparticular byproduct.

The high temperature for the high-k dielectric plasma etch in the secondchamber 220, about 100 to about 300 degrees Celsius, allows the high-kdielectric material to be etched faster than in a conventional lowtemperature plasma chamber. Further, at high temperature, the etchbyproduct is more volatile, without causing much change in the etch rateof polysilicon. Thus, the selectivity to polysilicon is high, allowinguse of an over etch of the high-k material of up to about 700%, or evengreater than about 700%.

Although shown with one chamber 210 for gate etching and one chamber 220for high-k dielectric etch, in some embodiments additional gate etchchambers and/or high-k dielectric etch chambers may be used. Further,although the above description is made with reference to etching offlash memory, embodiments and implementations of the present inventionare applicable to processing of any multilayer stack including high-kdielectric material, and where both low and high temperature plasma etchprocesses are desirable, or where a low temperature plasma etch combinedwith a reactive ion etch is beneficial.

While the invention herein disclosed has been described by the specificembodiments and implementations, numerous modifications and variationscould be made thereto by those skilled in the art without departing fromthe scope of the invention set forth in the claims.

1. A method for etching a flash memory high-k gate stack on a workpiece,the method comprising: a) etching a conductive material layer in a lowtemperature plasma chamber; b) etching a high-k dielectric layer in ahigh temperature plasma chamber; and c) transferring the workpiecebetween the low temperature plasma chamber and the high temperatureplasma chamber through a vacuum transfer chamber connecting the lowtemperature plasma chamber and the high temperature plasma chamber. 2.The method of claim 1, wherein etching the high-k material layercomprises plasma etching with a cathode temperature in a range aboveabout 150 degrees Celsius.
 3. The method of claim 2, wherein etching thehigh-k material layer comprises plasma etching with a cathodetemperature in a range above about 250 degrees Celsius.
 4. The method ofclaim 1, wherein etching the conductive material layer comprises etchingthe lower polysilicon layer with a cathode temperature below about 100degrees Celsius.
 5. The method of claim 4, wherein etching theconductive material layer comprises etching the lower polysilicon layerwith a cathode temperature below about 80 degrees Celsius.
 6. The methodof claim 1, wherein etching the conductive material layer comprisesetching a silicon comprising layer in the low temperature plasmachamber.
 7. The method of claim 6, wherein etching the conductivematerial layer comprises etching a polysilicon layer in the lowtemperature plasma chamber.
 8. The method of claim 7, wherein etchingthe polysilicon layer comprises etching with a cathode temperature belowabout 100 degrees Celsius.
 9. The method of claim 8, wherein etching thepolysilicon layer comprises etching with a cathode temperature belowabout 80 degrees Celsius.
 10. The method of claim 1, wherein etching theconductive material layer comprises etching a metal comprising layer inthe low temperature plasma chamber.
 11. The method of claim 10, whereinetching the conductive material layer comprises etching at least onelayer comprising: (a) tungsten; (b) tungsten nitride; or (c) tungstensilicide.
 12. A method for etching a wafer to form high-k dielectricflash memory devices, the method comprising: a) etching with a plasma ina low temperature chamber to define a control gate; b) etching with aplasma in the low temperature chamber to define a floating gate; c)etching a high-k interdielectric layer with plasma in a low temperaturechamber; and d) transferring the wafer through a vacuum chamber betweenthe high temperature chamber and the low temperature chamber betweenplasma etch processes.
 13. The method of claim 12, wherein etching inthe low temperature chamber comprises etching with a cathode temperatureless than about 100 degrees Celsius.
 14. The method of claim 12, whereinetching in the high temperature chamber comprises etching with a cathodetemperature greater than about 100 degrees Celsius.
 15. An integratedetch station for etching a high-k flash memory structure comprising: a)a conductive material etch chamber configured for plasma etch processingof a conductive material layer; b) a high-k etch chamber configured forplasma etch processing of a high-k dielectric layer; and c) a transferchamber connecting the low temperature chamber and the high temperaturechamber for transporting wafers between the low temperature chamber andthe high temperature chamber.
 16. The integrated etch station of claim15, wherein the high-k etch chamber is configured to etch in atemperature range greater than about 100 degrees Celsius, and whereinthe conductive material etch chamber is configured to etch in atemperature range below about 100 degrees Celsius.
 17. The integratedetch station of claim 15, wherein the high-k etch chamber is configuredto etch in a temperature range greater than about 250 degrees Celsius,and wherein the conductive material etch chamber is configured to etchin a temperature range below about 85 degrees Celsius.
 18. Theintegrated etch station of claim 15, wherein the high-k etch chamber isa reactive ion etch chamber.
 19. The integrated etch station of claim15, wherein the transfer chamber is a vacuum chamber.
 20. The integratedetch station of claim 15, wherein the conductive material etch chamberis configured for etching at least one of: (a) polysilicon; (b)tungsten; (c) tungsten nitride; or (d) tungsten silicide.